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1 ? fn8197.1 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. xdcp is a trademark of intersil americas inc. copyright intersil americas inc. 2005, 2006. all rights reserved all other trademarks mentioned are the property of their respective owners. x9428 low noise/low power/2-wire bus single digitally controlled potentiometer (xdcp?) features ? solid state potentiometer ? 2-wire serial interface ? register oriented format ?direct read/write/transfer wiper position ?store as many as four positions per potentiometer ? power supplies ?v cc = 2.7v to 5.5v ?v+ = 2.7v to 5.5v ?v? = -2.7v to -5.5v ? low power cmos ?standby current < 1a ?ideal for battery operated applications ? high reliability ?endurance?100,000 data changes per bit per register ?register data retention?100 years ? 4-bytes of nonvolatile memory ?10k resistor array ? resolution: 64 taps each potentiometer ? 16 ld soic, 14 ld tssop packages ? pb-free plus anneal available (rohs compliant) description the x9428 integrates a digitally controlled potentiometers (xdcp) on a monolithic cmos integrated microcircuit. the digitally controlled potentiometer is implemented using 63 resistive elements in a series array. between each element are tap points connected to the wiper terminal through switches. the position of the wiper on the array is controlled by the user through the 2-wire bus interface. each potentiometer has associated with it a volatile wiper coun ter register (wcr) and 4 nonvolatile data registers (dr0:dr3) that can be directly written to and read by the user. the contents of the wcr controls the position of the wiper on the resistor array through the switches. power-up recalls the contents of dr0 to the wcr. the xdcp can be used as a three-terminal potentiometer or as a two-terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing. block diagram r0 r1 r2 r3 wiper counter register (wcr) interface and control circuitry scl sda a0 a2 a3 v h /r h v l /r l data 8 v w /r w wp v cc v ss v+ v? data sheet april 26, 2006 n o t r e c o m m e n d e d f o r n e w d e s i g n s i n t e r s i l s u g g e s t s t h e i s l 2 2 3 1 6 o r i s l 2 2 3 1 9
2 fn8197.1 april 26, 2006 ordering information part number part marking v cc limits (v) potentiometer organization (k ) temp. range (c) package pkg. dwg. # x9428ws16* x9428ws 5 to 10% 10 0 to +70 16 ld soic (300 mil) m16.3 x9428ws16z* (note) x9428ws z 0 to +70 16 ld soic (300 mil) (pb-free) m16.3 x9428ws16i* x9428ws i -40 to +85 16 ld soic (300 mil) m16.3 x9428ws16iz* (note) x9428ws zi -40 to +85 16 ld soic (300 mil) (pb-free) m16.3 x9428wv14* x9428 w 0 to +70 14 ld tssop (4.4mm) m14.173 x9428wv14z* (note) x9428 z 0 to +70 14 ld tssop (4.4mm) (pb-free) m14.173 x9428wv14i* x9428 wi -40 to +85 14 ld tssop (4.4mm) m14.173 x9428wv14iz* (note) x9428 zi -40 to +85 14 ld tssop (4.4mm) (pb-free) m14.173 x9428ys16* x9428ys 2 0 to +70 16 ld soic (300 mil) m16.3 x9428ys16z* (note) x9428ys z 0 to +70 16 ld soic (300 mil) (pb-free) m16.3 x9428ys16i* x9428ys i -40 to +85 16 ld soic (300 mil) m16.3 x9428ys16iz* (note) x9428ys zi -40 to +85 16 ld soic (300 mil) (pb-free) m16.3 x9428yv14* x9428 y 0 to +70 14 ld tssop (4.4mm) m14.173 x9428yv14z* (note) x9428 yz 0 to +70 14 ld tssop (4.4mm) (pb-free) m14.173 x9428yv14i* x9428 yi -40 to +85 14 ld tssop (4.4mm) m14.173 x9428yv14iz* (note) x9428 yzi -40 to +85 14 ld tssop (4.4mm) (pb-free) m14.173 x9428ws16-2.7* x9428ws f 2.7 to 5.5 10 0 to +70 16 ld soic (300 mil) m16.3 x9428ws16z-2.7* (note) x9428ws zf 0 to +70 16 ld soic (300 mil) (pb-free) m16.3 x9428ws16i-2.7* x9428ws g -40 to +85 16 ld soic (300 mil) m16.3 x9428ws16iz-2.7* (note) x9428ws zg -40 to +85 16 ld soic (300 mil) (pb-free) m16.3 x9428wv14-2.7* x9428 wf 0 to +70 14 ld tssop (4.4mm) m14.173 x9428wv14z-2.7* (note) x9428 zf 0 to +70 14 ld tssop (4.4mm) (pb-free) m14.173 x9428wv14i-2.7* x9428 wg -40 to +85 14 ld tssop (4.4mm) m14.173 x9428wv14iz-2.7* (note) x9428 zg -40 to +85 14 ld tssop (4.4mm) (pb-free) m14.173 x9428ys16-2.7* x9428ys f 2 0 to +70 16 ld soic (300 mil) m16.3 x9428ys16z-2.7* (note) x9428ys zf 0 to +70 16 ld soic (300 mil) (pb-free) m16.3 x9428
3 fn8197.1 april 26, 2006 x9428ys16i-2.7* x9428ys g 2.7 to 5.5 2 -40 to +85 16 ld soic (300 mil) m16.3 x9428ys16iz-2.7* (note) x9428ys zg -40 to +85 16 ld soic (300 mil) (pb-free) m16.3 x9428yv14-2.7* x9428 yf 0 to +70 14 ld tssop (4.4mm) m14.173 x9428yv14z-2.7* (note) x9428 yzf 0 to +70 14 ld tssop (4.4mm) (pb-free) m14.173 x9428yv14i-2.7* x9428 yg -40 to +85 14 ld tssop (4.4mm) m14.173 x9428yv14iz-2.7* (note) x9428 yzg -40 to +85 14 ld tssop (4.4mm) (pb-free) m14.173 *add "t1" suffix for tape and reel. note: intersil pb-free plus anneal products em ploy special pb-free material sets; molding compounds/die attach materials and 100 % matte tin plate termination finish, which are rohs compliant and compatible with both snpb and pb-free soldering operations. intersil pb-free p roducts are msl classified at pb-free peak reflow temper atures that meet or exceed the pb-free requirements of ipc/jedec j std-020. ordering information (continued) part number part marking v cc limits (v) potentiometer organization (k ) temp. range (c) package pkg. dwg. # x9428
4 fn8197.1 april 26, 2006 pin descriptions host interface pins serial clock (scl) the scl input is used to clock data into and out of the x9428. serial data (sda) sda is a bidirectional pin used to transfer data into and out of the device. it is an open drain output and may be wire-ored with any number of open drain or open collector outputs. an open drain output requires the use of a pull-up resistor. for selecting typical values, refer to the guidelines for calculating typical values on the bus pull-up resistors graph. device address (a 0 , a 2 , a 3 ) the address inputs are used to set the least significant 3 bits of the 8-bit slave address. a match in the slave address serial data stream must be made with the address input in order to initiate communication with the x9428. a maximum of 8 devices may occupy the 2-wire serial bus. potentiometer pins r h /v h , r l /v l the r h /v h and r l /v l inputs are equivalent to the terminal connections on either end of a mechanical potentiometer. r w /v w the wiper outputs are equivalent to the wiper output of a mechanical potentiometer. hardware write protect input wp the wp pin when low prevents nonvolatile writes to the data registers. analog supply v+, v- the analog supply v+, v- are the supply voltages for the xdcp analog section. pin configuration pin names symbol description scl serial clock sda serial data a0, a2, a3 device address r h /v h , v l /r h potentiometer pins (terminal equivalent) r w /v w potentiometer pin (wiper equivalent) wp hardware write protection v+,v- analog and voltage follower v cc system supply voltage v ss system ground nc no connection v cc a2 r l /v l sda wp 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 v+ nc a0 nc a3 scl nc v- dip/soic x9428 v ss r h /v h r w /v w 1 2 3 4 5 6 7 14 13 12 11 10 9 8 tssop x9428 a2 r l sda wp v ss r h r w v cc v+ a0 nc a3 scl v- x9428
5 fn8197.1 april 26, 2006 principles of operation the x9428 is a highly integrated microcircuit incorporating a resistor array and its associated registers and counters and the serial interface logic providing direct communication between the host and the xdcp potentiometers. serial interface the x9428 supports a bidirectional bus oriented protocol. the protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. the device controlling the transfer is a master and the device being controlled is the slave. the master will alwa ys initiate da ta transfers and provide the clock for both transmit and receive operations. therefore, the x9428 will be considered a slave device in all applications. clock and data conventions data states on the sda line can change only during scl low periods (tlow). sda state changes during scl high are reserved for indicating start and stop conditions. start condition all commands to the x9428 are preceded by the start condition, which is a high to low transition of sda while scl is high (t high ). the x9428 continuously monitors the sda and scl lines for the start condition and will not respond to any command until this condition is met. stop condition all communications must be terminated by a stop condition, which is a low to high transition of sda while scl is high. acknowledge acknowledge is a software convention used to provide a positive handshake betwe en the master and slave devices on the bus to indica te the successful receipt of data. the transmitting device, either the master or the slave, will release the sda bu s after transmitting eight bits. the master generates a ninth clock cycle and during this period the receiver pulls the sda line low to acknowledge that it successfully received the eight bits of data. the x9428 will respond wit h an ackno wledge after recognition of a start cond ition and its slave address and once again after successful receipt of the command byte. if the command is followed by a data byte the x9428 will respond with a final acknowledge. array description the x9428 is comprised of a resistor array. the array contains 63 discrete resistive segments that are connected in series. the physical ends of the array are equivalent to the fixe d terminals of a mechanical potentiometer (v h /r h and v l /r l inputs). at both ends of the array and between each resistor segment is a cmos switch connected to the wiper (v w /r w ) output. within each individual array only one switch may be turned on at a time. these switches are controlled by the wiper counter register (wcr). the six bits of the wcr are decoded to select, and enable, one of sixty-four switches. the wcr may be written directly, or it can be changed by transferring the contents of one of four associated data registers into the wcr. these data registers and the wcr can be read and written by the host system. device addressing following a start condition the master must output the address of the slave it is accessing. the most significant four bits of t he slave address are the device type identifier (refer to figure 1 below). for the x9428 this is fixed as 0101[b]. figure 1. slave address the next four bits of the slave address are the device address. the physical device address is defined by the state of the a 0 , a 2 , a 3 inputs. the x9428 compares the serial data stream with the address input state; a successful compare of all four address bits is required for the x9428 to respond with an acknowledge. the a 0 , a 2 , a 3 inputs can be actively driven by cmos input signals or tied to v cc or v ss . 1 00 a3 a2 0 a0 device type identifier device address 1 x9428
6 fn8197.1 april 26, 2006 acknowledge polling the disabling of the inputs, during the internal nonvolatile write operation, can be used to take advantage of the typica l 5ms eeprom write cycle time. once the stop condition is issued to indicate the end of the nonvolatile write command the x9428 initiates the internal writ e cycle. ack polling can be initiated immediatel y. this involves issuing the start condition followed by the device slave address. if the x9428 is still busy with the write operation no ack will be returned. if the x9428 has completed the write operation an ack will be retu rned, and the master can then proceed with the next operation. flow 1. ack polling sequence instruction structure the next byte sent to the x9428 contains the instruction and register pointer info rmation. the four most significant bits are the instruction. the next four bits point to one of four associated registers. the format is shown below in figure 2. figure 2. instruction byte format the four high order bits define the instruction. the next two bits (r1 and r0) select one of the four registers that is to be acted upon when a register oriented instruction is issued. bits 0 and 1 are defined to be 0. four of the seven instructions end with the transmission of the instruction byte. t he basic sequence is illustrated in figure 3. these two-byte instructions exchange data between the wiper counter register and one of the data registers. a transfer from a data register to a wiper counter register is es sentially a write to a static ram. the response of the wi per to this action will be delayed t wrl . a transfer from the wiper counter register (current wiper positi on), to a data register is a write to nonvolatile memory and takes a minimum of t wr to complete. four instructions require a three-byte sequence to complete. these instructions transfer data between the host and the x9428; either between the host and one of the data registers or directly between the host and the wiper counter register. thes e instructions are: read wiper counter register (read the current wiper position of the selected pot), write wiper counter register (change current wiper position of the selected pot), read data register (read the contents of the selected nonvolatile register) and write data register (write a new value to the selected data register). the sequence of operations is shown in figure 4. nonvolatile write command completed enter ack polling issue start issue slave address ack returned? further operation? issue instruction issue stop no yes yes proceed issue stop no proceed i1 i2 i3 i0 r1 r0 0 0 register select instructions x9428
7 fn8197.1 april 26, 2006 figure 3. two-byte instruction sequence the increment/decrement command is different from the other commands. once the command is issued and the x9428 has responded with an acknowledge, the master can clock the selected wiper up and/or down in one segment steps; thereby, providing a fine tuning capability to the host . for each scl clock pulse (t high ) while sda is high, the selected wiper will move one resistor se gment towards the v h /r h terminal. similarly, for each scl clock pulse while sda is low, the selected wiper will move one resistor segment towards the v l /r l terminal. a detailed illustration of the sequen ce and timing for this operation are shown in figures 5 and 6 respectively. table 1. instruction set note: (7) 1/0 = data is one or zero s t a r t 0101a3a20a0 a c k i3 i2 i1 i0 r1 r0 0 0 a c k scl sda s t o p instruction instruction set operation i 3 i 2 i 1 i 0 r 1 r 0 x 1 x 0 read wiper counter register 1 0 0 1 0 0 0 0 read the contents of the wiper counter register write wiper counter register 1 0 1 0 0 0 0 0 write new value to the wiper counter register read data register 1 0 1 1 1/0 1/0 0 0 read the contents of the data register pointed to by r 1 - r 0 write data register 1 1 0 0 1/0 1/0 0 0 write new value to the data register pointed to by r 1 - r 0 xfr data register to wiper counter register 1 1 0 1 1/0 1/0 0 0 transfer the contents of the data register pointed to by r 1 - r 0 to its wiper counter register xfr wiper counter register to data register 1 1 1 0 1/0 1/0 0 0 transfer the contents of the wiper counter register to the data register pointed to by r 1 - r 0 increment/decrement wiper counter register 0 0 1 0 0 0 0 1/0 enable increment/decrement of the wiper counter register x9428
8 fn8197.1 april 26, 2006 figure 4. three-byte instruction sequence figure 5. increment/decrement instruction sequence figure 6. increment/decrement timing limits s t a r t 0 1 0 1 a3 a2 0 a0 a c k i3 i2 i1 i0 r1 r0 0 0 a c k scl sda s t o p a c k 0 0 d5 d4 d3 d2 d1 d0 s t a r t 0101a3a20a0 a c k i3 i2 i1 i0 r0 0 0 a c k scl sda s t o p x x i n c 1 i n c 2 i n c n d e c 1 d e c n r1 scl sda v w /r w inc/dec cmd issued voltage out t wrid x9428
9 fn8197.1 april 26, 2006 figure 7. acknowledge response from receiver figure 8. detailed potentiometer block diagram scl from data output from transmitter 1 89 start acknowledge master data output from receiver serial data path from interface circuitry register 0 register 1 register 2 register 3 serial bus input parallel bus input wiper counter register inc/dec logic up/dn clk modified scl up/dn v h /r h v l /r l v w /r w if wcr = 00[h] then v w /r w = v l /r l if wcr = 3f[h] then v w /r w = v h /r h 8 6 c o u n t e r d e c o d e (wcr) x9428
10 fn8197.1 april 26, 2006 detailed operation the potentiometer has a wiper counter register and four data registers. a detailed discussion of the register organization and array operation follows. wiper counter register the x9428 contains a wiper counter register. the wiper counter register can be envisioned as a 6-bit parallel and serial load counter with its outputs decoded to select one of sixty-four switches along its resistor array. the contents of the wcr can be altered in four ways: it may be writ ten directly by the host via the write wiper counter regi ster instruction (serial load); it may be written indirectly by transferring the contents of one of four associated data registers via the xfr data register instruct ion (parallel load); it can be modified one step at a time by the increment/decrement instruction. finally, it is loaded with the contents of its data register zero (dr0) upon power-up. the wcr is a volatile regist er; that is, its contents are lost when the x9428 is powered-down. although the register is automatically l oaded with the value in dr0 upon power-up, it should be noted this may be different from the value present at power-down. data registers the potentiometer has four nonvolatile data registers. these can be read or written directly by the host and data can be transferred between any of the four data registers and the wiper counter register. it should be noted all operations changing data in one of these registers is a nonvol atile operation and will take a maximum of 10ms. if the application does not require storage of multiple settings for the potentiometer, these registers can be used as regular memory locations that could possibly store system parameters or user preference data. register descriptions data registers, (6-bit), nonvolatile four 6-bit data registers for each xdcp. (eight 6-bit registers in total). ? {d5~d0}: these bits are for general purpose not volatile data storage or for storage of up to four different wiper values. the contents of data register 0 are automatically moved to the wiper counter register on power-up. wiper counter register, (6-bit), volatile one 6-bit wiper counter register for each xdcp. (four 6-bit registers in total.) ? {d5~d0}: these bits specif y the wiper position of the respective xdcp. the wiper counter register is loaded on power-up by the value in data register 0. the contents of the wcr can be loaded from any of the other data register or directly. the contents of the wcr can be saved in a dr. d5 d4 d3 d2 d1 d0 nv nv nv nv nv nv (msb) (lsb) wp5 wp4 wp3 wp2 wp1 wp0 vvvvvv (msb) (lsb) x9428
11 fn8197.1 april 26, 2006 instruction format notes: (1) ?mack?/?sack?: stands for the acknowledge sent by the master/slave. (2) ?a3 ~ a0?: stands for the device addresses sent by the master. (3) ?x?: indicates that it is a ?0? for testing pu rpose but physicall y it is a ?don?t care? condition. (4) ?i?: stands for the increment operation, sda held high during active scl phase (high). (5) ?d?: stands for the decrement operation, sd a held low during active scl phase (high). read wiper counter register (wcr) write wiper counter register (wcr) read data register (dr) write data register (dr) xfr data register (dr) to wiper counter register (wcr) s t a r t device type identifier device addresses s a c k instruction opcode s a c k wiper position (sent by slave on sda) m a c k s t o p 0101 a 3 a 2 0 a 0 10010000 00 w p 5 w p 4 w p 3 w p 2 w p 1 w p 0 s t a r t device type identifier device addresses s a c k instruction opcode s a c k wiper position (sent by master on sda) s a c k s t o p 0101 a 3 a 2 0 a 0 10100000 00 w p 5 w p 4 w p 3 w p 2 w p 1 w p 0 s t a r t device type identifier device addresses s a c k instruction opcode register addresses s a c k wiper position/data (sent by slave on sda) m a c k s t o p 0101 a 3 a 2 0 a 0 1011 r 1 r 0 00 00 w p 5 w p 4 w p 3 w p 2 w p 1 w p 0 s t a r t device type identifier device addresses s a c k instruction opcode register addresses s a c k wiper position/data (sent by master on sda) s a c k s t o p high-voltage write cycle 0101 a 3 a 2 0 a 0 1100 r 1 r 0 00 00 w p 5 w p 4 w p 3 w p 2 w p 1 w p 0 s t a r t device type identifier device addresses s a c k instruction opcode register addresses s a c k s t o p 0101 a 3 a 2 0 a 0 1101 r 1 r 0 00 x9428
12 fn8197.1 april 26, 2006 xfr wiper counter register (w cr) to data register (dr) increment/decrement wiper counter register (wcr) symbol table guidelines for calculating typical values of bus pull-up resistors s t a r t device type identifier device addresses s a c k instruction opcode register addresses s a c k s t o p high-voltage write cycle 0101 a 3 a 2 0 a 0 1110 r 1 r 0 00 s t a r t device type identifier device addresses s a c k instruction opcode s a c k increment/decrement (sent by master on sda) s t o p 0101 a 3 a 2 0 a 0 00100000 i/ d i/ d .... i/ d i/ d waveform inputs outputs must be steady will be steady may change from low to high will change from low to high may change from high to low will change from high to low don?t care: changes allowed changing: state not known n/a center line is high impedance 120 100 80 40 60 20 20 40 60 80 100 120 0 0 resistance (k) bus capacitance (pf) min. resistance max. resistance r max = c bus t r r min = i ol min v cc max =1.8k x9428
13 fn8197.1 april 26, 2006 absolute maximum ratings temperature under bias .................... -65 c to +135 c storage temperature ......................... -65 c to +150 c voltage on sda, scl or any address input with respect to v ss ......................... -1v to +7v voltage on v+ (referenced to v ss )........................ 10v voltage on v- (referenced to v ss )........................-10v (v+) - (v-) .............................................................. 12v any v h /r h ..............................................................v+ any v l /r l .................................................................v- lead temperature (soldering, 10 seconds)........ 300 c i w (10 seconds)................................................12ma comment stresses above those liste d under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only; functional operation of the device (at these or any ot her conditions above those listed in the operational sect ions of this specification) is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. analog characteristics (over recommended operating condi tions unless otherwise stated.) symbol parameter limits test conditions min. typ. max. unit end to end resistance tolerance 20 % power rating 50 mw 25c, each pot i w wiper current 6 ma r w wiper resistance 150 250 wiper current = 1ma, v cc = 3v 40 100 wiper current = 1ma, v cc = 5v v+ voltage on v+ pin x9428 +4.5 +5.5 v x9428-2.7 +2.7 +5.5 v- voltage on v- pin x9428 -5.5 -4.5 v x9428-2.7 -5.5 -2.7 v term voltage on any v h /r h or v l /r l pin v- v+ v noise -140 dbv ref: 1khz resolution (4) 1.6 % absolute linearity (1) 1 mi (3) v w(n)(actual) - v w(n)(expected) relative linearity (2) 0.2 mi (3) v w(n + 1 ) - [v w(n) + mi ] temperature coefficient of r total 300 ppm/ c ratiometric temperature coefficient 20 ppm/c c h /c l /c w potentiometer capacitances 10/10/25 pf see circuit #3, spice macromodel recommended operating conditions temp min. max. commercial 0 c+70 c industrial -40 c+85 c device supply voltage (v cc ) limits x9428 5v 10% x9428-2.7 2.7v to 5.5v x9428
14 fn8197.1 april 26, 2006 d.c. operating characteristics (over the recommended operating cond itions unless otherwise specified.) notes: (1) absolute linearity is utilized to determine actual wiper voltage versus expec ted voltage as determined by wiper positi on when used as a potentiometer. (2) relative linearity is utilized to deter mine the actual change in voltage between two successive tap posit ions when used as a potentiom- eter. it is a measure of the error in step size. (3) mi = rtot/63 or (r h - r l )/63, single pot (4) max. = all four arrays cascaded together, typical = individual array resolutions. endurance and data retention capacitance power-up timing power-up and power-down there are no restrictions on the power-up or power-down sequencing of the bias supplies v cc , v+, and v- provided that all three supplies reach their final values within 1msec of each other. however, at a ll times, the voltages on the potentiometer pins must be less than v+ and more than v-. the recall of the wiper pos ition from nonvolatile memory is not in effect until all su pplies reach their final value. notes: (5) this parameter is periodically sampled and not 100% tested (6) t pur and t puw are the delays required from the time the third (last) power supply (v cc , v+ or v-) is stable until the specific instruction can be issued. these parameters are periodically sampled and not 100% tested. (7) sample tested only. symbol parameter limits test conditions min. typ. max. unit i cc1 v cc supply current (nonvolatile write) 1maf scl = 400khz, sda = open, other inputs = v ss i cc2 v cc supply current (move wiper, write, read) 100 a f scl = 400khz, sda = open, other inputs = v ss i sb v cc current (standby) 1 a scl = sda = v cc , addr. = v ss i li input leakage current 10 a v in = v ss to v cc i lo output leakage current 10 a v out = v ss to v cc v ih input high voltage v cc x 0.7 v cc x 0.5 v v il input low voltage -0.5 v cc x 0.1 v v ol output low voltage 0.4 v i ol = 3ma parameter min. unit minimum endurance 100,000 data changes per bit per register data retention 100 years symbol test max. unit test conditions c i/o (5) input/output capacitance (sda) 8 pf v i/o = 0v c in (5) input capacitance (a0, a1, a2, a3, and scl) 6 pf v in = 0v symbol parameter min. typ. max. unit t pur (6) power-up to initiation of read operation 1 ms t puw (6) power-up to initiation of write operation 5 ms t r v cc (7) v cc power-up ramp rate 0.2 50 v/msec x9428
15 fn8197.1 april 26, 2006 a.c. test conditions equivalent a.c. load circuit circuit #3 spice macro model ac timing (over recommended operating conditions) i nput pulse levels v cc x 0.1 to v cc x 0.9 input rise and fall times 10ns input and output timing level v cc x 0.5 5v 1533 100pf sda output 2.7v 100pf 10pf r h r total c h 25pf c w c l 10pf r w r l symbol parameter min. max. unit f scl clock frequency 100 400 khz t cyc clock cycle time 2500 ns t high clock high time 600 ns t low clock low time 1300 ns t su:sta start setup time 600 ns t hd:sta start hold time 600 ns t su:sto stop setup time 600 ns t su:dat sda data input setup time 100 ns t hd:dat sda data input hold time 30 ns t r scl and sda rise time 300 ns t f scl and sda fall time 300 ns t aa scl low to sda data output valid time 900 ns t dh sda data output hold time 50 ns t i noise suppression time constant at scl and sda inputs 50 ns t buf bus free time (prior to any transmission) 1300 ns t su:wpa wp , a0, a1, a2 and a3 setup time 0 ns t hd:wpa wp , a0, a1, a2 and a3 hold time 0 ns x9428
16 fn8197.1 april 26, 2006 high-voltage wr ite cycle timing xdcp timing note: (8) a device must internally provide a hold time of at least 300ns for the sda signal in order to bridge the undefined regi on of the falling edge of scl. timing diagrams start and stop timing input timing output timing symbol parameter typ. max. unit t wr high-voltage write cycle time (store instructions) 5 10 ms symbol parameter min. max. unit t wrpo wiper response time after the third (last) power supply is stable 10 s t wrl wiper response time after instruction issued (all load instructions) 10 s t wrid wiper response time from an active scl/sc k edge (increment/decrement instruction) 10 s t su:sta t hd:sta t su:sto scl sda t r (start) (stop) t f t r t f scl sda t high t low t cyc t hd:dat t su:dat t buf scl sda t dh t aa x9428
17 fn8197.1 april 26, 2006 xdcp timing (for all load instructions) xdcp timing (for increment/decrement instruction) write protect and device address pins timing scl sda v w /r w (stop) lsb t wrl scl sda v w /r w t wrid wiper register address inc/dec inc/dec sda scl ... ... ... wp a0, a2, a3 t su:wpa t hd:wpa (start) (stop) (any instruction) x9428
18 fn8197.1 april 26, 2006 applications information basic configurations of electronic potentiometers application circuits v r v w /r w +v r i three terminal potentiometer; variable voltage divider two terminal variable resistor; variable current noninverting amplifier voltage regulator offset voltage adjustment comparator with hysteresis + ? v s v o r 2 r 1 v o = (1+r 2 /r 1 )v s r 1 r 2 i adj v o (reg) = 1.25v (1+r 2 /r 1 )+i adj r 2 v o (reg) v in 317 + ? v s v o r 2 r 1 v ul = {r 1 /(r 1 +r 2 )} v o (max) v ll = {r 1 /(r 1 +r 2 )} v o (min) 100k 10k 10k 10k -12v +12v tl072 + ? v s v o r 2 r 1 } } x9428
19 fn8197.1 april 26, 2006 application circuits (continued) inverting amplifier equivalent l-r circuit + ? v s v o r 2 r 1 z in = r 2 + s r 2 (r 1 + r 3 ) c 1 = r 2 + s leq (r 1 + r 3 ) >> r 2 + ? v s function generator } } v o = g v s g = - r 2 /r 1 r 2 c 1 r 1 r 3 z in + ? r 2 + ? r 1 } } r a r b frequency r 1 , r 2 , c amplitude r a , r b c attenuator filter + ? v s v o r 3 r 1 v o = g v s -1/2 g +1/2 g o = 1 + r 2 /r 1 fc = 1/(2 rc) r 2 r 4 all r s = 10k + ? v s r 2 r 1 r c v o x9428
20 fn8197.1 april 26, 2006 x9428 thin shrink small outlin e plastic packages (tssop) index area e1 d n 123 -b- 0.10(0.004) c a m bs e -a- b m -c- a1 a seating plane 0.10(0.004) c e 0.25(0.010) b m m l 0.25 0.010 gauge plane a2 notes: 1. these package dimensions are wi thin allowable dimensions of jedec mo-153-ac, issue e. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e1? does not include in terlead flash or protrusions. inter- lead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. dimension ?b? does not include dam bar protrusion. allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of ?b? dimen- sion at maximum material conditi on. minimum space between protru- sion and adjacent lead is 0.07mm (0.0027 inch). 10. controlling dimension: millimete r. converted inch dimensions are not necessarily exact. (angles in degrees) 0.05(0.002) m14.173 14 lead thin shrink small outline plastic package symbol inches millimeters notes min max min max a - 0.047 - 1.20 - a1 0.002 0.006 0.05 0.15 - a2 0.031 0.041 0.80 1.05 - b 0.0075 0.0118 0.19 0.30 9 c 0.0035 0.0079 0.09 0.20 - d 0.195 0.199 4.95 5.05 3 e1 0.169 0.177 4.30 4.50 4 e 0.026 bsc 0.65 bsc - e 0.246 0.256 6.25 6.50 - l 0.0177 0.0295 0.45 0.75 6 n14 147 0 o 8 o 0 o 8 o - rev. 2 4/06
21 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn8197.1 april 26, 2006 x9428 small outline plast ic packages (soic) notes: 1. symbols are defined in the ?mo series symbol list? in section 2.2 of publication number 95. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e? does not include inte rlead flash or protrusions. interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. the lead width ?b?, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. controlling dimension: millimeter. converted inch dimensions are not necessarily exact. index area e d n 123 -b- 0.25(0.010) c a m bs e -a- l b m -c- a1 a seating plane 0.10(0.004) h x 45 c h 0.25(0.010) b m m m16.3 (jedec ms-013-aa issue c) 16 lead wide body small outline plastic package symbol inches millimeters notes min max min max a 0.0926 0.1043 2.35 2.65 - a1 0.0040 0.0118 0.10 0.30 - b 0.013 0.0200 0.33 0.51 9 c 0.0091 0.0125 0.23 0.32 - d 0.3977 0.4133 10.10 10.50 3 e 0.2914 0.2992 7.40 7.60 4 e 0.050 bsc 1.27 bsc - h 0.394 0.419 10.00 10.65 - h 0.010 0.029 0.25 0.75 5 l 0.016 0.050 0.40 1.27 6 n16 167 0 8 0 8 - rev. 1 6/05

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